30extern uint32_t freertos_isr_enabled;
34#define portFLOAT float
35#define portDOUBLE double
37#define portSHORT short
38#define portSTACK_TYPE uint32_t
39#define portBASE_TYPE uint32_t
41#define portSTACK_GROWTH ( -1 )
42#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
43#define portBYTE_ALIGNMENT 4
44#define portPOINTER_SIZE_TYPE size_t
45typedef portSTACK_TYPE StackType_t;
46typedef int32_t BaseType_t;
47typedef uint32_t UBaseType_t;
49#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
50 typedef uint16_t TickType_t;
51 #define portMAX_DELAY ( TickType_t ) 0xffffU
52#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
53 typedef uint32_t TickType_t;
54 #define portMAX_DELAY ( TickType_t ) 0xffffffffU
55#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
56 typedef uint64_t TickType_t;
57 #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffU
59 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
63#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
64 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
67#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
70 #if ( configMAX_PRIORITIES > 32 )
71 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
75 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
76 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
80 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
88#define portDISABLE_INTERRUPTS() do {int ee; SYSTEM_DISABLE_ISR(freertos_isr_enabled);} while( 0 )
91#define portENABLE_INTERRUPTS() do {SYSTEM_ENABLE_ISR(freertos_isr_enabled);} while( 0 )
93#if ( configNUMBER_OF_CORES == 1 )
95 #define portENTER_CRITICAL() portDISABLE_INTERRUPTS()
98 #define portEXIT_CRITICAL() portENABLE_INTERRUPTS()
103 #define portCRITICAL_NESTING_IN_TCB 1
107 #define portENTER_CRITICAL vTaskEnterCritical
108 #define portEXIT_CRITICAL vTaskExitCritical
113 #define portENTER_CRITICAL_FROM_ISR vTaskEnterCriticalFromISR
114 #define portEXIT_CRITICAL_FROM_ISR vTaskExitCriticalFromISR
118extern void vPortYield(
void );
119#define portYIELD() vPortYield()
122#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
123#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
125#if ( configNUMBER_OF_CORES > 1 )
127 #define portGET_CORE_ID() 0
130 #define portSET_INTERRUPT_MASK() 0
133 #define portCLEAR_INTERRUPT_MASK( x ) ( ( void ) ( x ) )
136 #define portYIELD_CORE( x ) do {} while( 0 )
140 #define portGET_TASK_LOCK( xCoreID ) do {} while( 0 )
144 #define portRELEASE_TASK_LOCK( xCoreID ) do {} while( 0 )
148 #define portGET_ISR_LOCK( xCoreID ) do {} while( 0 )
152 #define portRELEASE_ISR_LOCK( xCoreID ) do {} while( 0 )
Access parts of the base system.